Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
A flash memory is a type of memory that can be erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed on a random basis by charging the floating gate. The data in a cell is determined by the presence or absence of the charge in the floating gate. The charge can be removed from the floating gate by a block erase operation.
Each memory cell can be programmed as a single bit per cell (i.e., single level cell—SLC) or multiple bits per cell (i.e., multilevel cell—MLC). Each cell's threshold voltage (Vt) determines the data that is stored in the cell. For example, in a single bit per cell, a Vt of 0.5V can indicate a programmed cell while a Vt of −0.5V might indicate an erased cell. The multilevel cell may have multiple Vt windows that each indicates a different state. Multilevel cells take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage distribution for the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of voltage ranges assigned to the cell.
It is important that the Vt distributions be sufficiently spaced apart so as to reduce the possibility of a higher voltage of one distribution overlapping a lower Vt of the next distribution. The overlap can occur due to noise or temperature variations of the integrated circuit. One way to create larger gaps between the various threshold voltage distributions is to make the distributions themselves narrower. This can be a problem since memory cells program at different rates.
Faster memory cells may be programmed before the slower cells since the faster cells require fewer programming pulses. This can result in the Vt distribution for the faster cells being different and/or closer to other distributions than slower cells due to the wider distributions created by faster cells.
One way to solve this problem is illustrated in U.S. Pat. No. 6,643,188 to Tanaka et al. and assigned to Toshiba and SanDisk Corporation. Tanaka et al. disclose a two-step programming method that uses first and second step verify voltages. Once a threshold voltage for a memory cell being programmed reaches the first step verify voltage, a write control voltage is changed for all cells being programmed. This slows down the programming of all the memory cells.
One problem with this approach is that it reduces programming throughput. Reducing the programming speed of all of the cells being programmed increases the time it takes to program all of the cells, whether they are a fast cell or a slow cell.
Another method that may be used to create narrower distributions is to adjust the programming pulse step voltage as the cell approaches a programmed state. However, this also slows the programming for all of the bits, thus reducing programming throughput. This is especially true for the higher distributions that require additional programming pulses that take longer to reach due to the smaller increment.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to generate narrow Vt distributions without reducing the programming throughput of the memory device.